xPU architecture atlas
Block diagrams of the CPUs, GPUs and systems on chip behind the VLA Hub benchmarks. They show how cores group into clusters and share caches, how a GPU stacks clusters of SMs over one L2, where the NPU sits, and what memory feeds them all. Every chip is drawn in one grammar, so a Raspberry Pi 5 reads the same way as an RTX 5090.
CPUs and GPUs are built as the same kind of nest. Units are grouped into clusters, clusters share a cache, and at the bottom sits a register that holds a few 32-bit lanes. They differ in where the width is: a CPU core runs a few threads, each with wide registers, while a GPU runs thousands of narrow threads and switches between them to hide memory latency. Each panel below zooms into the framed block of the panel before it.
vla.simd's micro-kernel keeps one output tile of every matrix product in vector registers. AVX2 and NEON each give it 512 bytes of architectural registers, cut in different ways, and that alone sets the tile shape. A GPU partition has 128 times as much register storage, because it keeps dozens of threads resident at once.
12 + 2 + 1 = 15 of 16 ymm registers
Sixteen 256-bit registers. Twelve accumulators hold the tile, two hold a row of weights, and one holds a broadcast activation that is reused down the whole tile.
16 + 4 + 4 = 24 of 32 v registers
Thirty-two 128-bit registers, half as wide. A row needs four registers, and each row reads its activations lane by lane from its own vector, so a taller tile would spill.
up to 255 registers per thread
The register file is the largest on-chip memory of an SM. A warp that stalls on memory is swapped for another whose registers are already loaded, so latency is hidden by switching between warps, not by holding a tile.
Counts are architectural registers. Cores rename them onto larger physical files, which the kernel cannot address. Colours: accumulators, weights, broadcast or laned activations, free. Tiles and register budgets are from the vla.simd paper.
The chip on the left, one unit of it on the right. A frame with a solid ring is a processor that VLA Hub measured, tagged with the engine and backend that ran on it. Blocks are not drawn to scale.
The units that do the work, the cache nearest to them, the last level before DRAM, and the memory bandwidth that feeds them. Bandwidth spans a factor of a hundred across these devices and is drawn on a log scale.
| Device | Compute units | Vector / matrix | Per-unit cache | Last level | Memory | Bandwidth | Measured |
|---|
Desktop and laptop CPUs show the fastest memory the platform supports. The machines VLA Hub measured may run slower modules. SoC bandwidth is shared by every processor on the chip.
Each diagram is a logical map: which units exist, how they are grouped, and which caches each group shares. It is not a floorplan, and block sizes are not to scale.
Units that exist on the die but are disabled in this product are dashed. Which SMs or cores are fused off varies from chip to chip, so they are drawn at the end of a row.
From vendor datasheets, product pages and architecture whitepapers. Where vendors publish no figure, the source is a die analysis or a measurement by Chips and Cheese and similar sites. Each device links its sources.
Bandwidth figures that no vendor publishes are calculated from bus width and data rate. Where sources disagree, the card says so.
A ringed frame is a processor that has rows on VLA Hub: vla.cpp through ggml backends (CUDA, Metal, SYCL, OpenVINO, Hexagon, CPU) or vla.simd through its own AVX2 and NEON kernels.
The register tiles come from the vla.simd paper, which chooses them per instruction set.
Vendors publish only part of each chip, so some of these diagrams rest on die analyses and measurements. Open an issue on GitHub to correct a diagram, with a source if you have one, or to ask for a processor to be drawn.